WHICH PARTY WILL MADE GOVT IN 2014 BJP OR CONGRESS

Wednesday, 11 December 2013

Click on the "Start count!" button above to start the timer. The input field will count forever, starting at 0. Click on the "Stop count!" button to stop the counting. Click on the "Start count!" button to start the timer again.

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Click on the button above. The input field will count forever, starting at 0.

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Click on the button above. The input field will tell you when two, four, and six seconds have passed.
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Click on the button above. The input field will tell you when two, four, and six seconds have passed.

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Monday, 21 October 2013

Visit www.facebook.com! If you set the target attribute to "_blank", the link will open in a new browser window/tab.
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Wednesday, 9 October 2013

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Monday, 8 April 2013

INDEX  
 S. No.
1.
2.
3.
Topic
Introduction to VHDL.
Design all types of gates using VHDL.
Write VHDL code for the following circuits. Check the wave
form and Hardware generated.
    (a) Multiplexer
(b) Demultiplexer
4.
Write VHDL code for the following circuits. Check the wave
form and Hardware generated.
          (a) Encoder
(b) Decoder
5.
6.
7.
Write VHDL code for Code Converter. Check the wave form
and Hardware generated.
Write VHDL code for Comparator. Check the wave form and
Hardware generated.
Write VHDL code for the following circuits. Check the wave
form and Hardware generated.
          (a) Half Adder
(b) Full Adder
8.
9.
Write VHDL code for Flip Flops. Check the wave form and
Hardware generated.
Write VHDL code for the following circuits. Check the wave
form and Hardware generated.
          (a) Half Subtractor
(b) full Subtractor
10.
Write VHDL code for Counter. Check the wave form and
Hardware generated.
T. Sign
                                       



                                                DIGITA SYSTEM DESIGN     


PROGRAM 1-INTRODUCTION TO VHDL
VHDL is Very High Speed Integrated Circuit Hardware Description Language.
Downloaded the ModelSim version 10.0.
When opened an IMPORTANT information box appeared and click on Jumpstart.
For creation of project click on Create a Project
1 Gopal Kumar | CSE-6th Semester | Roll No: 06


Project name is entered.
After selecting jumpstart we created a new file…
2 Gopal Kumar | CSE-6th Semester | Roll No: 06


We named the file with the same name as that of the name defined in the entity.
A file is created named and_behave.vhd.
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Edit the file and wrote the program.
Compile the program by selecting Compile Selected.
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Start the simulation.
Simulation is started
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and_behave entity is selected
Now we will enter the the input to get desired output.
6 Gopal Kumar | CSE-6th Semester | Roll No: 06


All items in region are added to wave.
Selected signal is forced and 1st input value is entered.
7 Gopal Kumar | CSE-6th Semester | Roll No: 06


2nd input value is entered.
For output NoForce is selected and we get the desired output.
8 Gopal Kumar | CSE-6th Semester | Roll No: 06


PROGRAM 2 - Design all types of gates using VHDL.
AND GATE
library ieee;
use ieee.std_logic_1164.all;
entity and_behave is
port (a,b :in std_logic;
      y: out std_logic);
end and_behave;
architecture and_behave_a of and_behave is
begin
process (a,b)
begin
y<=a and b;
end process;
end and_behave_a;
9 Gopal Kumar | CSE-6th Semester | Roll No: 06


OR          GATE   
library ieee;     
use ieee.std_logic_1164.all;   
entity or_behave is
port (a,b :in std_logic;
      y: out std_logic);
end or_behave;
architecture or_behave_a of or_behave is
begin
process (a,b)
begin
y<=a or b;
end process;
end or_behave_a;
Waveform :-
               
               
               
10 Gopal Kumar | CSE-6th Semester | Roll No: 06


               
               
NOT      GATE   
library ieee;
use ieee.std_logic_1164.all;
entity not_behave is
port (a:in std_logic;
     y: out std_logic);
end not_behave;
architecture not_behave_a of not_behave is
begin
process (a)
begin
y<=not a;
end process;
end not_behave_a;
Waveform :-
               
               
               
               
11 Gopal Kumar | CSE-6th Semester | Roll No: 06


NAND   GATE   
library ieee;
use ieee.std_logic_1164.all;
entity nand_behave is
port (a,b :in std_logic;
      y: out std_logic);
end nand_behave;
architecture nand_behave_a of nand_behave is
begin
process (a,b)
begin
y<=a nand b;
end process;
end nand_behave_a;
Waveform :-
               
               
               
               
12 Gopal Kumar | CSE-6th Semester | Roll No: 06


NOR      GATE   
library ieee;
use ieee.std_logic_1164.all;
entity nor_behave is
port (a,b :in std_logic;
      y: out std_logic);
end nor_behave;
architecture nor_behave_a of nor_behave is
begin
process (a,b)
begin
y<=a nor b;
end process;
end nor_behave_a;
Waveform :-
13 Abhineet Jayaraj | CSE-6th Semester | Roll No: 02


XOR       GATE   
library ieee;
use ieee.std_logic_1164.all;
entity xor_behave is
port (a,b :in std_logic;
      y: out std_logic);
end xor_behave;
architecture xor_behave_a of xor_behave is
begin
process (a,b)
begin
y<=a xor b;
end process;
end xor_behave_a;
Waveform :-
14 Gopal Kumar | CSE-6th Semester | Roll No: 06


PROGRAM 3 – Write VHDL program for the following circuits. Check the waveform &
hardware generated:-
(a) Multiplexer
(b) DeMultiplexer
(a) Multiplexer:-
library ieee;
use ieee.std_logic_1164.all;
entity mux21 is
port (i:in std_logic_vector(1 downto 0) ;
s:in std_logic;
y:out std_logic);
end mux21;
architecture mux21_a of mux21 is
begin
y<=i(0) when s='0' else
i(1);
end mux21_a;
Waveform :-
15 Gopal Kumar | CSE-6th Semester | Roll No: 06


(b) DeMultiplexer:-
library ieee;
use ieee.std_logic_1164.all;
entity demux12_behave is
port (i,s:in std_logic;
    d:out std_logic_vector(1 downto 0));
end demux12_behave;
architecture demux12_behave_a of demux12_behave is
begin
process(s,i)
begin
case s is
when '0'=>d(0)<=i; d(1)<='Z';
when others=>d(0)<='Z'; d(1)<=i;
end case;
end process;
end demux12_behave_a;
Waveform :-
16 Gopal Kumar | CSE-6th Semester | Roll No: 06


PROGRAM 4 – Write   VHDL    program             for          the         following            circuits.                Check   the         wave    
form     &             hardware                generated:‐       
(a)Encoder       
(b)Decoder       
Encoder
library ieee;
use ieee.std_logic_1164.all;
entity encoder83pr_ifelse is
port (s:in std_logic_vector(7 downto 0);
    y:out std_logic_vector(2 downto 0));
end encoder83pr_ifelse;
architecture encoder83pr_ifelse_a of encoder83pr_ifelse is
begin
process (s)
begin
if(s(7)='1') then
y<="111";
elsif(s(6)='1') then
y<="110";
elsif(s(5)='1') then
y<="101";
elsif(s(4)='1') then
y<="100";
elsif(s(3)='1') then
y<="011";
elsif(s(2)='1') then
y<="010";
elsif(s(1)='1') then
y<="001";
else
y<="000";
end if;
end process;
end encoder83pr_ifelse_a;
17 Gopal Kumar | CSE-6th Semester | Roll No: 06


Waveform :-
18 Gopal Kumar | CSE-6th Semester | Roll No: 06


Decoder
library ieee;
use ieee.std_logic_1164.all;
entity decoder38_ws is
port (s:in std_logic_vector(2 downto 0);
    sim:/decoder38_ws/s sim:/decoder38_ws/y y:out std_logic_vector(7 downto 0));
end decoder38_ws;
architecture decoder38_ws_a of decoder38_ws is
begin
with s select
y<= "00000001" when "000",
   "00000010" when "001",
   "00000100" when "010",
   "00001000" when "011",
   "00010000" when "100",
   "00100000" when "101",
   "01000000" when "110",
   "10000000" when others;
end decoder38_ws_a;
Waveform :-
19 Gopal Kumar | CSE-6th Semester | Roll No: 06


PROGRAM 5 - Write VHDL code for Code Converter. Check the wave form and Hardware
                                 generated.
Code convertor (BCD to 7 segment)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity bcd is
port(i:in std_logic_vector(0 to 3);
    y: out std_logic_vector(0 to 6));
end bcd;
architecture bcd_df of bcd is
begin
y<= "1111110" when i="0000" else
   "0110000" when i="0001" else
   "1101101" when i="0010" else
   "1111001" when i="0011" else
   "0110011" when i="0100" else
   "1011011" when i="0101" else
   "1110000" when i="0111" else
   "1111111" when i="1000" else
   "1111011" when i="1001" ;
  end bcd_df;
Simulation         Result   :‐
20 Gopal Kumar | CSE-6th Semester | Roll No: 06


PROGRAM 6 – Write   VHDL    program             for          the         Comparator.     Check   the                wave                    
form     &             hardware                generated.         
COMPARATOR
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY comp4b IS
PORT(A,B:IN BIT_VECTOR(3 DOWNTO 0);
F1,F2,F3:OUT BIT);.
END ENTITY;
ARCHITECTURE behav OF comp4b IS
BEGIN
PROCESS(A,B)
BEGIN
IF(A(3)='0' AND B(3)='1')THEN F3<='1';F2<='0';F1<='0';
ELSIF(A(3)='1' AND B(3)='0')THEN F1<='1';F2<='0';F3<='0';
ELSE
IF(A(2)='0' AND B(2)='1')THEN F3<='1';F2<='0';F1<='0';
ELSIF(A(2)='1' AND B(2)='0')THEN F1<='1';F2<='0';F3<='0';
ELSE
IF(A(1)='0' AND B(1)='1')THEN F3<='1';F2<='0';F1<='0';
ELSIF(A(1)='1' AND B(1)='0')THEN F1<='1';F2<='0';F3<='0';
ELSE
IF(A(0)='0' AND B(0)='1')THEN F3<='1';F2<='0';F1<='0';
ELSIF(A(0)='1' AND B(0)='0')THEN F1<='1';F2<='0';F3<='0';
ELSE
F2<='1';F1<='0';F3<='0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END behav;.
21 Gopal Kumar | CSE-6th Semester | Roll No: 06


Simulation         Result   :‐
               
22 Gopal Kumar | CSE-6th Semester | Roll No: 06


PROGRAM 7 – Write   VHDL    program             for          the         following            circuits.                Check   the         wave                    
form     &             hardware                generated:‐       
(a)Half Adder
(b) Full Adder 
Half adder
library  ieee;     
use         ieee.std_logic_1164.all; 
entity    ha_behave           is            
port       (a,b:in   std_logic               ;              
                                                                                                sum,carry:out    std_logic);           
end        ha_behave;        
architecture       ha_behave_a       of            ha_behave                is            
begin    
process(a,b)      
begin    
sum<=a                xor         b;           
carry<=a              and        b;           
end        process;              
end        ha_behave_a;    
Waveform :-
23 Gopal Kumar | CSE-6th Semester | Roll No: 06


FULL ADDER
library ieee;
use ieee.std_logic_1164.all;
entity fa_behave is
port (a,b,c:in std_logic ;
    sum,carry:out std_logic);
end fa_behave;
architecture fa_behave_a of fa_behave is
begin
process(a,b,c)
begin
sum<=a xor b xor c;
carry<=(a and b) or (b and c) or (a and c) ;
end process;
end fa_behave_a;
Waveform :-
24 Gopal Kumar | CSE-6th Semester | Roll No: 06


PROGRAM 8 – Write   VHDL    program             for          all           the         Flip        Flop.      Check                the         wave                    
form     &             hardware                generated.         
D FLIPFLOP:-
VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffD IS
PORT(D,CLK,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffD;
ARCHITECTURE behav OF ffD IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1' AND CLK 'EVENT;
IF(RESET='1') THEN Q<='0';QINV<='1';
ELSIF D='1' THEN Q<='1';QINV<='0';
ELSE Q<='0';QINV<='1';
END IF;
END PROCESS;
END behav;
               
Simulation         Result   :‐
25 Gopal Kumar | CSE-6th Semester | Roll No: 06


T –FLIPFLOP:-
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity tff is
port (T, CLK, RST : in std_logic;
Q,QB : out std_logic);
end tff;
architecture behav of tff is
begin
process (clk, RST) begin if (RST = '1') then
Q <= '1'; QB <= '0';
elsif (clk'event and clk = '1') then
QB <= T;
Q <= not T;
end if;
end process;
end behave;
Simulation         Result   :‐
26 Gopal Kumar | CSE-6th Semester | Roll No: 06


JK FLIP FLOP
library ieee;
use ieee.std_logic_1164.all;
entity jkff is
port(j,k,clk,sd_l,rd_l:in bit;
q,q_l:inout bit);
end jkff;
architecture jkff_arch of jkff is
begin
process(clk)
begin
if(rd_l='0' and sd_l='1')
then q<='0';
elsif(rd_l='1' and sd_l='0')
then q<='1';
elsif(rd_l='1' and sd_l='1')
then if(clk'event and clk='0')
then
if(j='0' and k='1') then q<='0';
elsif(j='1' and k='0') then q<='1';
elsif(j='0' and k='0') then q<=q;
elsif(j='1' and k='1') then q<=not q;
end if;
end if;
Simulation         Result   :‐
27 Gopal Kumar | CSE-6th Semester | Roll No: 06


PROGRAM 9 – Write   VHDL    program             for          the         following            circuits.                Check   the         wave                    
form     &             hardware                generated:‐       
(a)Half Subtractor
(b) Full Subtractor       
HALF subtractor
library  ieee;     
use         ieee.std_logic_1164.all; 
entity    hs_behave           is            
port       (a,b:in   std_logic               ;              
                                                                                                diff,bor:out         std_logic);           
end        hs_behave;         
architecture       hs_behave_a       of            hs_behave                is            
signal    d:std_logic;        
begin    
process(a,b)      
begin    
diff<=a  xor         b;           
bor<=d and        b;           
d<=not a;           
end        process;              
end        hs_behave_a;                     
Simulation         Result   :‐
28 Gopal Kumar | CSE-6th Semester | Roll No: 06


FULL Subtractor
library ieee;
use ieee.std_logic_1164.all;
entity fs_behave is
port (a,b,c:in std_logic ;
    diff,bor:out std_logic);
end fs_behave;
architecture fs_behave_a of fs_behave is
begin
process(a,b,c)
begin
diff<=a xor b xor c;
bor <=((not a) and b) or (not(a xor b) and c) ;
end process;
end fs_behave_a;
Simulation         Result   :‐
29 Gopal Kumar | CSE-6th Semester | Roll No: 06


PROGRAM 10 – Write                VHDL    program             for          all           the         Counter.                Check   the         wave                    
form     &             hardware                generated.         
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity cntr is
port(clock : in STD_LOGIC;
reset : in STD_LOGIC;
qout : out STD_LOGIC_VECTOR(3 downto 0));
end cntr;
architecture cntr_arc of cntr is
signal temp_count: std_logic_vector(3 downto 0);
begin
process(clock,reset)
begin
if(clock='1' and clock'event)then if(reset='1')then
temp_count<=(others=>'0');
else
temp_count<= temp_count + 1;
end if;
end if;
end process;
qout<=temp_count;
end cntr_arc;
Simulation         Result   :‐
30 Gopal Kumar | CSE-6th Semester | Roll No: 06

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